Integrated circuits are an integral part of any electronic device. A variety of integrated circuits are often used together to enable the operation of the electronic device. While integrated circuits are typically designed for a particular application, one type of integrated circuit which enables flexibility is a programmable logic device (PLD). A PLD is designed to be user-programmable so that users may implement logic designs of their choices. One type of PLD is the Complex Programmable Logic Device (CPLD). A CPLD includes two or more “function blocks” having a two-level AND/OR structure connected together and to input/output (I/O) resources by an interconnect switch matrix. Another type of PLD is a field programmable gate array (FPGA). In a typical FPGA, an array of configurable logic blocks (CLBs) is coupled to programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a hierarchy of programmable routing resources. For both of these types of programmable logic devices, the functionality of the device is controlled by configuration data bits of a configuration bitstream provided to the device for that purpose. The configuration data bits may be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Clock signals are also used for a variety of purposes in digital circuits, both on board level systems and integrated circuit (IC) devices. An integrated circuit such as a PLD typically receives one or more external reference clock signals to generate one or more internal clock signals to operate internal digital circuits. In synchronous systems, global clock signals are used to synchronize various circuits across the board or IC device. While multiple clock generating circuits may be used to generate the multiple clock signals, clock generating circuits typically consume a large amount of chip space. Therefore, most systems use one clock generating circuit to generate a first clock signal called a reference clock signal, and a specialized circuit to derive other clock signals from the reference clock signal. For example, clock dividers are used to generate one or more clock signals of lower clock frequencies from the reference clock signal. Typically, clock dividers divide the frequency of the reference clock signal by an integer value D. Conversely, clock multipliers are used to generate one or more clock signals of higher clock frequencies, for example M times the reference clock signal. Combining clock multipliers with clock dividers provides clock circuits which may generate one or more clock signals having frequencies that are fractional values of the frequency of the reference clock signal, commonly called frequency synthesis. For example, if the generated clock frequency has a ratio of M/D that is 7/2 of the reference clock frequency, then the two clock edges of the generated clock signal and the reference clock signal should be in concurrence every 7 cycles of the generated clock signal and every 2 cycles of the reference clock signal. That is, a pulse train comprising 7 clock cycles of the generated clock signals is compared with a reference pulse train of two clock cycles of the reference clock signal to determine whether the generated clock signal is at the correct frequency, as is well know in the art. A clock signal may also be generated having an M/D ratio of 1, where the generated clock signal would have different properties.than the reference clock signal, such as a spread spectrum clock signal.
Electromagnetic interference (EMI) is electromagnetic radiation which is generated by electrical circuits carrying rapidly changing signals, such as a clock signal. EMI causes unwanted interference or noise to be induced in other circuits, and therefore degrades the performance of the other circuits. Spread-spectrum clock generation is used in the design of synchronous digital systems to reduce the spectral density of the EMI that these clock signals generate. A synchronous digital system is one that is driven by a clock signal and, because of its periodic nature, has a narrow frequency spectrum. In particular, perfect clock signal would have all its energy concentrated at a single frequency. However, such a clock signal may exceed the regulatory limits for electromagnetic interference, such as limits established by the Federal Communications Commission (FCC).
To avoid this problem, spread-spectrum clocking is commonly used to reshape the system's electromagnetic emissions to comply with the electromagnetic compatibility regulations. Spread spectrum clocking spreads the energy of the clock signal over a large frequency band, defined by a frequency deviation, at certain modulation frequencies. Generating a spread spectrum clock signal effectively reduces the electrical and magnetic field strengths that are measured within a narrow window of frequencies within the frequency band. That is, spread-spectrum clocking distributes the energy so that it falls into a large number of the receiver's frequency bands, where there is not enough energy in any one band to exceed the regulatory limits.
A spread spectrum clock signal may be a center spread clock signal, where the frequency of the clock signal varies between a frequency which is greater than the desired generated clock signal and a frequency which is less than the desired generated clock signal. Alternatively, a spread spectrum clock signal may be a side spread clock signal, where the frequency of the clock signal varies between the desired generated clock signal and a frequency which is either greater than or less than the desired generated clock signal. In generating a spread spectrum clock signal, it is desirable to generate the highest energy spread with the lowest frequency deviation.
While spread spectrum clocking is a common technique to gain regulatory approval for a device, conventional circuits for generating a spread spectrum clock signal are often limited. For example, many spread spectrum clocking techniques use phase locked loops (PLLs). Digital circuits used as a front-end of a PLL often increase the “cycle-to-cycle” jitter, commonly defined as the difference in length between any two adjacent clock periods of the clock signal. Conventional devices implementing spread spectrum clocks also provide little flexibility for parameters related to the generated signal. Further, for devices having more than one clock signal, a separate spread spectrum clocking chip may be required for each clock signal.
Accordingly, there is a need for an improved method of and circuit for generating a spread spectrum clock signal.